Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA

This paper proposes a post-filtering system for improving the quality of depth maps 3D projection on FPGA. We propose to implement Weighted Least Square (WLS) filter Field-programmable Gate Array (FPGA), which can predict disparities, cannot be measured, by using values neighboring pixels. In our design, we optimized architecture WLS at algorithm level. For hardware acceleration, use High-Level Synthesis (HLS) description accelerate algorithm. To break through bottleneck brought limited memory resources FPGA, used UltraScale Architecture Memory Resources (URAM) board and reduced consumption Block RAMs (BRAM) from 140% 80%. Through approach, improve map FPGA named M-KUBOS. And, smooth with 130 MHz operational frequency M-KUBOS speed 10 frames per second (FPS), achieves 76.43% performance acceleration compared software execution ARM Cortex A9 1.2 GHz clock.